Introduction to FinFET (2024)

FinFET is an innovative design derived from the traditional standard Field-Effect Transistor (FET). In the traditional transistor structure, the gate that controls the flow of current can only control the on and off of the circuit on one side of the gate, which belongs to a planar architecture. In the FinFET architecture, the gate is a fork-shaped 3D structure similar to a fish fin, and the on and off of the circuit can be controlled on both sides of the circuit. This design can greatly improve circuit control and reduce leakage, and can also greatly shorten the gate length of the transistor.

Catalog

ⅠFinFETworking principle

FinFET is called a Fin field-effect transistor, which is a new complementary metal oxide semiconductor transistor. The inventor of this technology is Professor Hu Zhengming of the University of California, Berkeley.

FinFET working principle diagram

As shown in the figure, the main difference between FinFet and planar MOSFET structure is that its channel is made up of tall and thin fins raised on an insulating substrate. The source and drain are at both ends, and the three gates are close to their sidewalls and tops, whichare used to assist current control. This fin-shaped structure increases the area ofthe gate surrounding the channel and strengthens the gate's control over the channel, which can effectively alleviate the short channel effect in planar devices. Itgreatly improves circuit control and reduction of leakage current and can also greatly shorten the gate length of the transistor. Because of this feature, Finfet does not need to be highly doped in the channel, so it can effectively reduce the impurity ion scattering effect and improve the channel carrier mobility.

ⅡFinFETstructure

The electron microscope photograph of FinFET

As shown in the figure, the main feature of FinFET is that the channel region is a fin-shaped semiconductor surrounded by the gate. The length of the fin along with the source and drain direction is the channel length. The gate-wrapped structure enhances the control ability of the gate and provides better electrical control of the channel, thereby reducing the leakage current and suppressing the short channel effect. However, there are many kinds of FinFETs, and different FinFETs have different electrical characteristics. The following will be introduced separately according to the substrate type, channel direction, number of gates, and gate structure. According to the FinFET substrate, FinFET can be divided into two types. One is SOI FinFET and the other is bulk FinFET. The bulk FinFET is formed on a bulk silicon substrate. Due to different manufacturing processes, bulk silicon substrates have the advantages of low defect density and low cost compared with SOI substrates. In addition, due to the lower thermal conductivity of the buried oxygen layer in the SOI substrate, the heat dissipation performance of the bulk silicon substrate is also better than that of the SOI substrate.

Bulk FinFET and SOI FinFET have similar parasitic resistance and parasitic capacitance, which can provide similar power performance at the circuit level. However, the light fin-doped FinFET of the SOI substrate exhibits lower junction capacitance, higher mobility, and electrical performance of voltage gain than bulk FinFET.

The characteristics of this structure are as follows:

1) Ultra-thin Si fin to suppress short channel effect;

2) The two gates are self-aligned, and are also aligned with the source and drain;

3) Growing polysilicon in the source and drain regions can reduce parasitic resistance;

4) The short (50nm) Si fin is a quasi-planar structure;

5) The post-gate fabrication process is compatible with low-temperature and high-K gate dielectrics.

ⅢFinFETapplications

The practical strained germanium quantum well channels P-type metal oxide semiconductor (MoS) fin field-effect transistor shows that the fin field effect transistor and the tri-gate structure have the possibility of being applied to 7mm and 5nm CMOS devices.

Since the development of CMOS devices to 90m technology, embedding the silicon germanium source and drain in the device has been a common method to produce strained silicon-enhanced P-type MOS devices. The reduction in device size makes the space for strain in the source and drain extremely limited. It is difficult to further miniaturize fin-type field-effect transistors with thin structures. The direct application of high-strain materials to the channel will be a viable way for CMOS devices to continue to be miniaturized.

The Belgian Microelectronics Research Center has grown a highly strained germanium channel on the relaxed silicon germanium buffer layer. This method has proved that this method can increase the channel electron mobility and has a good potential for scaling down the channel size. The use of fin replacement technology to fabricate strained germanium channel devices is very useful for realizing integration with other devices on conventional silicon substrates. The transconductance peak value of strained germanium P-channel fin field-effect transistor built on the silicon germanium channel buffer layer is 1.3ms/μm at 0.5V source-drain voltage, with good short-channel control as low as 60mm gate length ability. The sub-threshold slope transconductance of the device is higher than the announced relaxed germanium fin field-effect transistor.

ⅣFinFETadvantages

FinFET devices have obvious advantages over traditional planar transistors. First of all, the FinFeTchannel is generally lightly doped or even undoped, which avoids the scattering effect of discrete doping atoms. Compared with heavily doped planar devices, carrier mobility will be greatly improved. In addition, compared with traditional planar CMOS, FinFET devices have absolute advantages in suppressing sub-threshold current and gate leakage current. The body fin structure of FinFET's double gate or half ring gate increases the gate control area of the channel, which greatly enhances the gate control ability, andeffectively suppresses the short channel effect, and reduces the sub-threshold leakage current. Due to the suppression of the short channel effect and the enhancement of the gate control capability, the finFET device can use a thicker gate oxide than the traditional one, so that the gate leakage current of the FinFET device will also be reduced. Obviously, FinFET is better than PDSOI. And, because FinFET is similar in process to CMOS technology, it is technically easier to implement. So it has been used by many large companies in the manufacture of small-size ICs.

ⅤTechnology development status

At the beginning of 2011, Intel launched a commercial FinFET, which is used in its 22nm node process. Major semiconductor foundries such as TSMC have also begun plans to launch their own FinFET. Since 2012, FinFeT has begun to advance to the 20mm node and 14nm node.

Future development focus: P-type doping is implemented in silicon germanium to improve device performance, optimize the thickness of the silicon passivation layer on germanium, and improve the winding effect of the trench gate. This study verified that the germanium-germanium silicon heterogeneous quantum well device with a fin-type field effect transistor structure can not only provide strain capacity but also enhance channel control.

The use of fin replacement technology realizes the application of II-V group materials to the structure of CMOS devices. This research result makes it possible to use germanium to form the channel of the CMOS device through the fin replacement process. This is the key technology to realize monolithic heterogeneous integration and develop CMOS devices and system-on-chips.

The Belgian Microelectronics Research Center's next-generation FinFET research is part of its core CMOS project.

Future: GAA-FET (Gate-All-Around)will replace FinFET

The first commercialization of FinFET at the 22nm node has brought a disruptive change to the manufacturing of transistors-micro switches in the "brains" of chips. Compared with the previous planar transistors, the channels formed by the "fins" in contact with the gate on three sides are easier to control. However, as the problems faced by 3nm and 5nm technology nodes continue to accumulate, the effectiveness of FinFETs has reached its limit.

planar FET,FinFET and GAA-FET

1) The Dilemma of Transistor Scaling

At each technology node, equipment manufacturers can reduce device area, cost, and power consumption and achieve performance improvements by shrinking transistors. This method is also called PPAC (power, performance, area, cost) scaling. However, further reduction in the size of the FinFET will limit the drive current and electrostatic control capabilities.

In planar transistors, the channel width can be increased to drive more current and increase the turn-on and turn-off speed. However, with the development of CMOS design, the track height of standard cells continues to decrease, which leads to the limitation of the size of the "fin", and single-fin devices manufactured based on nodes below 5nm will not be able to provide sufficient drive current.

In addition, although three sides of the "fin" are controlled by the gate, there is still one side that is uncontrolled. As the gate length is shortened, the short channel effect will be more obvious, and more current will leak through the non-contact part of the bottom of the device. Therefore, devices with a smaller size will not be able to meet the power consumption and performance requirements.

2) Replace fins with nano flakes

The Gate-All-Around(GAA) is an improved transistor structure in which all sides of the channel are in contact with the gate so that continuous scaling can be achieved. A transistor with this structure is called a Gate-All-Around(GAA) transistor, and many variants of this type of transistor have appeared.

Early GAA devices used a method of vertically stacking nanoflakes, that is, the horizontally placed flakes were placed in the gate separately from each other. Compared with FinFET, the channel under this method is easier to control. And unlike FinFETs that must line up multiple fins to increase current, GAA transistors only need to vertically stack a few nanosheets and allow the gate to wrap the channel to obtain a stronger current-carrying capacity. In this way, only need to scale these nanoflakes can be adjusted to meet the specific performance requirements of the transistor size.

FinFET and GAA FET

However, like fins, as technology advances and feature sizes continue to decrease, the width and spacing of the fins will continue to shrink. When the width of the flakes is almost equal to the thickness, these nanoflakes will look more like "nanowires."

3) Manufacturing challenges

Although the concept of nano-sheets is simple, it brings many new challenges to actual manufacturing. Some of the manufacturing problems stem from the structure, while others are related to the new materials needed to meet the scaling goals of PPAC.

Specifically, the main challenge in construction stems from the complexity of the structure. To fabricate a GAA transistor, it is first necessary to use Si and SiGe epitaxial layers alternately to form a superlattice and use it as the basis of the nanosheet structure, and then to sink a dielectric isolation layer into the interior,and remove the sacrificial layer of the channel by etching. The space left after the sacrificial layer is removed, including the space between the nanosheets, needs to be filled with a gatemade of dielectric and metal. Future gates are likely to use new metal materials, among which cobalt has entered the evaluation stage; ruthenium, molybdenum, nickel, and various alloys have also been taken into consideration by manufacturers.

4) Continuous progress

GAA transistors will eventually replace FinFETs, and the nanosheets in them will gradually develop into nanowires. The GAA structure should be able to apply to all advanced process nodes currently included in the plan.

Starting from the earliest planar structure, transistor architecture has made considerable progress and effectively promoted the development of intelligent interconnection, all of which were unimaginable by the early industry pioneers. With the advent of fully enclosed gate transistors, we are also eagerly looking forward to it bringing more amazing end-user equipment and functions to the world.